The present invention relates to a dynamic semiconductor memory and, more particularly to a dynamic type random access memory employing MOS transistors.
Dynamic type random access memories (DRAMs) have been widely utilized as large capacity memories.
A DRAM is usually structured such that a plurality of memory cells are arranged in a matrix form of rows and columns. Word lines are arranged in rows while digit lines are arranged in columns. Also, sense amplifiers are provided for the respective digit lines for reading or refreshing the content of selected memory cells. A signal read-out from a memory cell via a digit line is applied to a sense amplifier which amplifies the read-out data. A memory cell employing one transistor and one capacitor is generally utilized in a DRAM.
In recent years, memory capacity has been enlarged and the number of memory cells has been greatly increased. This also means an increase in the number of word lines intersecting the digit lines and an increase in the number of memory cells connected to the respective digit lines. Accompanied by the increase in the memory cells connected to each digit line increases, the electrostatic capacitance of the digit line also is increased. Therefore, input signal level to a sense amplifier is often reduced, resulting in malfunction of the sense amplifier. For the purpose of compensating for such reduction in the input signal level to the sense amplifier, a so-called "shared amplifier" technique has been proposed. According to this technique, a pair of digit lines are physically split into two pairs of digit lines and a selected one of the pairs of digit lines is electrically connected to a sense amplifier. Thus, the capacitance of the split digit lines is greatly reduced to increase the read-out signal at the digit line. This shared sense amplifier technique is disclosed in U.S. Pat. No. 4,366,559 issued to Misaizu et al.
Information stored in the memory cells disappears over time, and hence the memory cells have to be subjected to a refresh operation at a contant time interval so as to hold the information. This refresh is achieved by cyclically selecting one word line and amplifying data stored the memory cells connected to the selected word line and repeating the above cycle for all the word lines. Therefore, for a large capacity memory and a large number of word lines, the number of the above cycles is large. This means that the total time period for refreshing all the memory cells is large and hence the utilization ratio of the memory is lowered.